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[VHDL-FPGA-Verilog] CPLD_CCD

Description: 实现基于CPLD的CCD采集系统设计源码-based CPLD CCD Acquisition System Design FOSS
Platform: | Size: 66560 | Author: 周宇 | Hits:

[VHDL-FPGA-Verilog] Hardware_Interface_Implementation_FPGA

Description:
Platform: | Size: 1508352 | Author: Dai Fenzhou | Hits:

[VHDL-FPGA-Verilog] DMADMA_fanli

Description: 详细介绍nios DMA范例,很有帮助的.-Nios DMA detailed examples, very helpful.
Platform: | Size: 6144 | Author: 朱蒙蒙 | Hits:

[Other] lpcinterface

Description: lpc源代码verilog实现的。操作low pin count设备-LPC realize the Verilog source code. Operation of low pin count devices
Platform: | Size: 1024 | Author: 毛军捷 | Hits:

[VHDL-FPGA-Verilog] CPRI

Description:
Platform: | Size: 933888 | Author: 郭坚 | Hits:

[VHDL-FPGA-Verilog] PCI_BUS_Verilog

Description: PCI_bus_Verilog example
Platform: | Size: 3072 | Author: 展望 | Hits:

[VHDL-FPGA-Verilog] multi16

Description: verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Platform: | Size: 7168 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] arbiter

Description: 一个用verilog编写的总线仲裁程序。多个设备共享总线，不同设备的优先级是变化的，保证每个设备都有公平的使用总线的机会。-Verilog prepared a bus with arbitration proceedings. Multiple devices share the bus, the priority of different devices is changing to ensure that each device will have a fair opportunity to use the bus.
Platform: | Size: 3072 | Author: bao rui | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

[Other] PCI_VHDL

Description: 从PCI时序分析入手，重点阐述了PCI通用的状态机设计，说明了用VHDL语言来实现本PIC通信状态机的软件设计以及进行MaxPlusII验证的程序和方法。用该方法所设计的接口既可支持PCI常规传输，又可支持PCI猝发传输。-PCI timing analysis from the start, focusing on general-purpose PCI state machine design, described by VHDL language to achieve the PIC communications state machine software design as well as MaxPlusII verification procedures and methods. Designed using this method can support the PCI interface of conventional transmission, but also support the PCI burst transfers.
Platform: | Size: 182272 | Author: lilei | Hits:

[Program doc] hi3512

Description: 用vhdl语言实现的pci通信协议，对初学者有一定的借鉴意义！-pci_vhdl
Platform: | Size: 1626112 | Author: 白棉田 | Hits:

[File Format] congxianchaoshengshujucaiji

Description: 在研究超声检测技术以及高频信号采集和处理技术发展趋势和PCI总线的特点基 础上，提出了一种基于PCI总线的超声数据采集卡的实现方案。在硬件方面，系统由模 数转换模块、数据缓冲模块、接口模块和逻辑控制模块等四个功能模块构成，着重研究 了接口芯片PCI9052的数据传输方式，采用原理图+VHDL的方法设计了板卡的内部控 制逻辑和数据缓冲模块，并进行了相关的时序仿真和逻辑验证。-Ultrasonic testing in research and high-frequency signal acquisition and processing technology development trends and characteristics based on the PCI bus, a PCI bus based on ultrasound data acquisition was implemented. In hardware, the system consists of analog-digital conversion module, the data buffer module, interface module and the logic control module and other modules of four functions, and focused on the interface chip PCI9052 data transmission, using the method schematic+ VHDL design of the board The internal control logic and data buffer module, and make the relevant time simulation and logic verification.
Platform: | Size: 4976640 | Author: 姚木 | Hits:

[VHDL-FPGA-Verilog] eeprom_out

Description: vhdl code for card pci to fpga
Platform: | Size: 4096 | Author: sina | Hits:

[VHDL-FPGA-Verilog] pci_744

Description: vhdl pci core implemtation
Platform: | Size: 4348928 | Author: vport | Hits:

[VHDL-FPGA-Verilog] pci_gr

Description: vhdl code for Simple PCI target interface
Platform: | Size: 5120 | Author: JP | Hits:

[VHDL-FPGA-Verilog] Ms32pci

Description: PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL! Author is Ovidiu Lupas! MASTER model generates PCI compliant signals checks Target signal compliance with PCI checks data received from Target for correctness generates assertion reports if Target signals are not PCI compliant TARGET model generates PCI compliant signals checks Master signal compliance with PCI checks data received from Master for correctness generates assertion reports if Master signals are not PCI compliant Description The models are boardlevel simulation models and are useful in the testing phase of the PCI cores design. The models are 32 bit, 33 MHz PCI compliant but are easy upgradable to 64 bit, 66 MHz. The models are free you can redistribute them and/or modify them under the terms of the GNU General Public License as published by the Free Software Foundation either version 2 of the License, or (at your option) any later version. The models are distributed in the hope that they will be useful, but WITH
Platform: | Size: 6144 | Author: kity | Hits:

[VHDL-FPGA-Verilog] src

Description: 基于pci协议的开发板端pci接口vhdl程序 包括数据存储等-the source code of pci interface
Platform: | Size: 30720 | Author: KSniper | Hits:

[VHDL-FPGA-Verilog] pci_code

Description: PCI接口程序，采用VHDL语言，包括主程序和testbench文件-PCI INTERFACE IN VHDL
Platform: | Size: 89088 | Author: AricSnow | Hits:

[VHDL-FPGA-Verilog] pcixpci_corev702errfix

Description: Vhdl madule for pci core for altera design
Platform: | Size: 167936 | Author: alexsandre | Hits:

[VHDL-FPGA-Verilog] control_interface

Description: vhdl中的pci接口控制部分，完成pci接口读写-vhdl pci interface control section in
Platform: | Size: 2048 | Author: mu | Hits:
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